1. Field of the Invention
The present invention relates to a semiconductor memory device including a plurality of memory cells, in which data can be written into these memory cells and data can be read out from these memory cells. More specifically, the present invention relates to a semiconductor memory device capable of performing a read only operation for a part of data.
2. Description of the Related Art
For example, a liquid crystal display device includes a liquid crystal panel, liquid crystal drivers, A/D converter, an image memory (semiconductor memory device) and the like. A picture signal is input to the A/D converter, and an image data output from the A/D converter is once stored in the image memory. The image data in the image memory is supplied to the liquid crystal driver so as to drive the liquid crystal panel, thereby displaying the image in a display screen of the liquid crystal panel.
In order to protect liquid crystals in the liquid crystal panel, even when no picture signal is input and no image data exist in the image memory, the liquid crystal panel must be kept driven by supplying high-level or low-level data to the liquid crystal driver.
Therefore, the image memory stores predetermined read only data which is to be supplied to the liquid crystal driver when no image data exist, and the data can be read out any time. Thus, the image memory includes not only a memory area where writing and reading of data are possible, but also a memory area where reading of data is only possible.
A static random access memory (SRAM) as shown in FIG. 4 is one example of such semiconductor devices. In FIG. 4, memory cells M are disposed in a matrix of 4.times.R (row.times.column). Each of the memory cells M includes a pair of load resistances R1 and R2 connected to a power supply voltage (not shown), a pair of N channel transistors T11 and T12 for holding data, and a pair of N channel transistors T21 and T22 for inputting and outputting data. Sources of the N channel transistors T11 and T12 for holding data are grounded. Drains and gates of the transistors T11 and T12 are cross-coupled. These N channel transistors T11 and T12 are operated complementarily. When data is supplied through the N channel transistors T21 and T22, the N channel transistors T11 and T12 continue to hold the data.
In each of the memory cells M in the Rth column, the load resistance R2 is omitted. As a result, a high-level potential is retained by the N channel transistor T11, and a low-level potential is retained by the N channel transistor T12, thereby fixing the data in each of the memory cells M in the Rth column.
In other words, each of the memory cells M in the Rth column serves as a read only memory (ROM), and each memory cell M in the columns other than the Rth column serves as a RAM.
Word signal lines X1 to X4 are provided along the rows in a matrix arrangement of the memory cells M, respectively. For each row, the word signal line is connected to a gate of each of the N channel transistors T21 and T22 in each of the memory cells M.
Along the columns, bit signal lines B1 to BR and /B1 to /BR are provided, respectively. For each of the columns, a pair of bit signal lines B and /B are connected to drains of the N channel transistors T21 and T22 in each of the memory cells M, respectively. For each of the columns, the pair of the bit signal lines B and /B are connected to common data signal lines CD and /CD through column selecting transistors T31 and T32, respectively. For each of the columns, current is supplied to the pair of the bit signal lines B and /B through load transistors T41 and T42, respectively.
Moreover, for each of the columns, the pair of the bit signal lines B and /B are connected to each other via a transistor T51. Prior to writing of data into each of the memory cells M and reading of data out from each of the memory cells M, an address transition detecting signal ATD from an address generating circuit AD shown in FIG. 5 is supplied to a gate of the transistor T51. The transistor T51 is temporarily turned ON, thereby equalizing charges in each of the bit signal lines B and /B.
A row decoder X-DEC inputs address signals Ax1 and Ax2 for designating rows of the matrix arrangement from the address generating circuit AD shown in FIG. 5. The row decoder X-DEC selects the rows in a sequential manner so that the word signal lines X1 to X4 are sequentially switched to and set at a high level. Every time each of the word signal lines X1 to X4 is switched to be high level in a sequential manner, N channel transistors T21 and T22 in each of the memory cells M in the corresponding row are turned ON through the word signal line. As a result, for each of the memory cells M, data signals D and /D are transmitted from the respective N channel transistors T11 and T12 to the respective bit signal lines B and /B.
A column decoder Y-DEC inputs address signals Ay1, Ay2, and Ay3 for designating columns of the matrix arrangement from the address generating circuit AD shown in FIG. 5. The column decoder Y-DEC selects each of the columns in a sequential manner so that column selecting signals y are supplied to gates of the column selecting transistors T31 and T32 in the selected column, thereby turning ON these column selecting transistors T31 and T32. When column selecting transistors T31 and T32 in the selected column are turned ON, the data signals D and /D on the bit signal lines B and /B are transmitted to the common data signal lines CD and /CD.
Current is supplied to the common data signal lines CD and /CD through a group of load transistors TL.
Each of sense amplifiers SP1 and SP2 responds to a delay address transition detecting signal AE from a delay circuit Del (shown in FIG. 6). As a result, differential amplification of the data signals D and /D on the common data signal lines CD and /CD is performed so as to output these data signals D and /D to read data signal lines RD and /RD.
An output circuit OUT forms a data signal DOUT from data signals D and /D on the read data signal lines RD and /RD, and outputs the data signal DOUT to an output signal line out.
An input circuit IN includes an operation driving unit Dr0 for driving a transferring transistor T61 and coupling transistors T71 and T72. The transferring transistor T61 is turned ON or OFF in response to a write enabling signal /WE and connects an input terminal in to a write data signal line /DI. The coupling transistors T71 and T72 are turned ON or OFF in response to a column selecting signal yR in the last column of the matrix arrangement, i.e., the Rth column, and the write enabling signal /WE. The coupling transistors T71 and T72 connect the write data signal line /DI to the common data signal lines CD and /CD.
A timing of each of the signals in the above-described semiconductor memory device will be described with reference to FIG. 7 and the circuit diagram of FIG. 4. As can be seen from FIG. 7, an initiation signal /CS is made to be low level so that the sense amplifiers SP1, SP2, the output circuit OUT and the input circuit IN are made to be in an operatable state.
Under this condition, when each of the address signals Ax1, Ax2, Ay1, Ay2, and Ay3 is generated, the address transition detecting signal ATD becomes high level for a predetermined period of time from a point t1. As a result, for each column, the pair of bit signal lines B and /B are connected to each other via the transistor T51, thereby equalizing charges of the bit signal lines B and /B.
At a point t2, the row decoder X-DEC makes one of the word signal lines X1 to X4 high level in response to the address signals Ax1 and Ax2. For each memory cell M in one row, the row decoder X-DEC outputs the data signals D and /D from the memory cell M to the bit signal lines B and /B.
At a point t3 which is slightly after the point t2, the column decoder Y-DEC selects one of the columns of the matrix arrangement in response to the address signals Ay1, Ay2, and Ay3. The column selecting signals y are supplied to the column selecting transistors T31 and T32 in the selected column so that these column selecting transistors are turned ON and the data signals D and /D on the bit signal lines B and /B are transmitted to the common data signal lines CD and /CD.
Moreover, at a point t4, differential amplification of the data signals D and /D on the common data signal lines CD and /CD is performed by the sense amplifiers SP1 and SP2 in response to the delay address transition detecting signal AE so as to output these data signals D and /D to the read data signal lines RD and /RD. These data signals D and /D are output to the output signal line out as a data signal DOUT via the output circuit OUT.
Such a data reading operation is also performed when the address of each memory cell M in the Rth column is generated. The data signals D and /D in the each memory cell M in the Rth column are transmitted to the bit signal lines B and /B, the common data signal lines CD and /CD, the read data signal lines RD and /RD, and the output signal line out in a sequential manner.
On the other hand, when data is written, an out enabling signal /OE becomes high level at a point t5, thereby inhibiting the operation of the output circuit OUT. For a predetermined period of time from a point t6, the write enabling signal /WE is kept at a low level so that the transferring transistor T61 of the input circuit IN is turned ON. As a result, the input terminal in is connected to the write data signal line /DI. At this time, if the memory cells M in the columns other than the Rth column are designated, the column selecting signal yR designating the Rth column becomes low level, and a write data enabling signal DIE becomes high level. As a result, the coupling transistors T71 and T72 in the input circuit IN are turned ON so that the write data signal line /DI is connected to the common data signal lines CD and /CD. Consequently, the data signal is introduced from the input terminal in to the common data signal lines CD and /CD, thereby enabling the writing of data.
However, if each of the memory cells M in the Rth column, which serves as a ROM, is designated and the column selecting signal yR is high level, the write data enabling signal DIE becomes low level. As a result, the coupling transistors T71 and T72 in the input circuit IN are turned OFF, thereby blocking data signals from the input terminal in.
However, since the above-described conventional semiconductor memory device partially contains the memory cells M in a less-frequently-used Rth column, i.e., ROMs, the area occupied by the memory cells M of the semiconductor memory device is increased.